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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:56:01 04/05/2010 
-- Design Name: 
-- Module Name:    i2s_clkgen - RTL 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description:    Vzorkovaci hodiny pro I2S DAC
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity i2s_clkgen is
    Port ( clk : in  STD_LOGIC;			-- systemove hodiny (50MHz)
           RESET : in  STD_LOGIC;		-- systemovy reset (aktivni pri 1)
           RATE : out  STD_LOGIC);		-- Samplovaci frq = MCLK / 384 ( @ 50 MHz => 130.20833 kHz, @ 16MHz => 41.6666 kHz )
end I2S_clkgen;

architecture RTL of i2s_clkgen is

begin

	process(clk)
		variable clk_counter : STD_LOGIC_VECTOR(8 downto 0);
	begin
		if (clk'event and clk = '1') then
			if RESET = '1' or clk_counter = CONV_STD_LOGIC_VECTOR(383,9) then
				RATE <= '1';
				clk_counter := (others=>'0');
			else
				clk_counter := clk_counter + 1;
				RATE <= '0';
			end if;
		end if;
	end process;

end RTL;

