----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:37:16 04/05/2010 
-- Design Name: 
-- Module Name:    i2s_sound - RTL 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 		I2S sound (emulace SN76489AN + audio vystup pro CTC0 pres I2S DAC)
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity i2s_sound is
    Port ( clk : in  STD_LOGIC;									-- systemove hodiny ( 50MHz )
			  RESET : in  STD_LOGIC;								-- systemovy reset (aktivni pri 1)
			  DATA : in  STD_LOGIC_VECTOR (7 downto 0);		-- datova sbernice z MZ800
			  WE : in STD_LOGIC;										-- povolen zapis dat do PSG (aktivni pri 1)
			  CTC0_PWM : in STD_LOGIC;								-- zdroj hodin z casovace CTC0
			  I2S_MCLK : out  STD_LOGIC;							-- I2S master clock - JA(4), DIGI1_0
			  I2S_SCLK : out  STD_LOGIC;							-- I2S serial clock - JA(6), DIGI1_2
			  I2S_LRCK : out  STD_LOGIC;							-- I2S left/right clock - JA(5), DIGI1_1
			  I2S_SDAT : out  STD_LOGIC);							-- I2S data - JA(7), DIGI1_3
end i2s_sound;

architecture RTL of i2s_sound is

	-- generator I2S vystupu
	component i2s_driver
	Port (
		clk : in  STD_LOGIC;									-- systemove hodiny ( 16 MHz, 50 MHz)
      RESET : in  STD_LOGIC;								-- systemovy reset (aktivni pri 1)
      L_DATA : in  STD_LOGIC_VECTOR (23 downto 0);	-- binarni komplement pro levy kanal
      R_DATA : in  STD_LOGIC_VECTOR (23 downto 0);	-- binarni komplement pro pravy kanal
      LOAD : out  STD_LOGIC;								-- signal k nabirani dat (vzorkovani)
      I2S_MCLK : out  STD_LOGIC;							-- I2S master clock
      I2S_SCLK : out  STD_LOGIC;							-- I2S serial clock
      I2S_LRCK : out  STD_LOGIC;							-- I2S left/right clock
      I2S_SDAT : out  STD_LOGIC);						-- I2S data
	end component;

	component audiogen
	Port (
		clk : in  STD_LOGIC;										-- vtupni hodiny audio generatoru ( 50 MHz )
      SAMPLE_ENABLE : in  STD_LOGIC;						-- povoleni nabirani vzorku (sample rate)
		DATA : in  STD_LOGIC_VECTOR (7 downto 0);			-- datova sbernice z MZ800
		WE : in STD_LOGIC;										-- povolen zapis dat do PSG (aktivni pri 1)
      CTC0_PWM : in STD_LOGIC;								-- zdroj zvuku casovace CTC0
      L_DATA : out  STD_LOGIC_VECTOR (23 downto 0);	-- vystupni audio data pro levy kanal
      R_DATA : out  STD_LOGIC_VECTOR (23 downto 0));	-- vystupni audio data pro pravy kanal
	end component;


	signal iLOAD : STD_LOGIC;
	signal iL_DATA : STD_LOGIC_VECTOR (23 downto 0);
	signal iR_DATA : STD_LOGIC_VECTOR (23 downto 0);

begin


	-- generator I2S vystupu
	i2s: i2s_driver
	Port map (
		clk		=> clk,										-- systemove hodiny (16 MHz, 50 MHz)
		RESET		=> RESET,									-- systemovy reset (aktivni pri 1)
		L_DATA	=> iL_DATA,									-- binarni komplement pro levy kanal
		R_DATA	=> iR_DATA,									-- binarni komplement pro pravy kanal
		LOAD		=> iLOAD,									-- signal k nabirani dat (vzorkovani)
		I2S_MCLK	=> I2S_MCLK,								-- I2S master clock
		I2S_SCLK	=> I2S_SCLK,								-- I2S serial clock
		I2S_LRCK	=> I2S_LRCK,								-- I2S left/right clock
		I2S_SDAT	=> I2S_SDAT									-- I2S data
	);



	-- pripojeni audio generatoru
	agen: audiogen
	Port map (
		clk				=> clk,								-- vtupni hodiny audio generatoru (50 MHz)
		SAMPLE_ENABLE	=> iLOAD,							-- povoleni nabirani vzorku (sample rate)
		DATA				=> DATA,								-- datova sbernice z MZ800
		WE					=> WE,								-- povolen zapis dat do PSG (aktivni pri 1)
		CTC0_PWM			=> CTC0_PWM,						-- zdroj zvuku z casovace CTC0
		L_DATA			=> iL_DATA,							-- vystupni audio data pro levy kanal
		R_DATA			=> iR_DATA							-- vystupni audio data pro pravy kanal
	);

	
end RTL;

