----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:27:12 04/03/2010 
-- Design Name: 
-- Module Name:    square_generator - RTL
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 	 Generator s obdelnikovym prubehem
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity square_generator is
    Port ( CK443K : in  STD_LOGIC;								-- src hodiny (443 kHz)
           ATTEN : in  STD_LOGIC_VECTOR(3 downto 0);		-- uroven tlumeni hlasitosti kanalu  
           DIVIDER : in  STD_LOGIC_VECTOR(9 downto 0);	-- nastaveni delicky generatoru
           WAVE : out  SIGNED(23 downto 0)					-- vystupni data v binarnim komplementu +, -, nebo 0
			);
end square_generator;

architecture RTL of square_generator is

signal iWAVE : STD_LOGIC_VECTOR(23 downto 0);
signal iVOLUME : STD_LOGIC_VECTOR(7 downto 0);

begin

	-- z urovne tlumeni urcime hlasitost
	iVOLUME 	<= CONV_STD_LOGIC_VECTOR( 0, 8 ) when ATTEN = "1111" else	-- vypnuto
					CONV_STD_LOGIC_VECTOR( 15, 8 ) when ATTEN = "1110" else	-- nejtissi
					CONV_STD_LOGIC_VECTOR( 31, 8 ) when ATTEN = "1101" else
					CONV_STD_LOGIC_VECTOR( 47, 8 ) when ATTEN = "1100" else
					CONV_STD_LOGIC_VECTOR( 63, 8 ) when ATTEN = "1011" else
					CONV_STD_LOGIC_VECTOR( 79, 8 ) when ATTEN = "1010" else
					CONV_STD_LOGIC_VECTOR( 95, 8 ) when ATTEN = "1001" else
					CONV_STD_LOGIC_VECTOR( 127, 8 ) when ATTEN = "1000" else
					CONV_STD_LOGIC_VECTOR( 143, 8 ) when ATTEN = "0111" else
					CONV_STD_LOGIC_VECTOR( 159, 8 ) when ATTEN = "0110" else
					CONV_STD_LOGIC_VECTOR( 175, 8 ) when ATTEN = "0101" else
					CONV_STD_LOGIC_VECTOR( 191, 8 ) when ATTEN = "0100" else
					CONV_STD_LOGIC_VECTOR( 207, 8 ) when ATTEN = "0011" else
					CONV_STD_LOGIC_VECTOR( 223, 8 ) when ATTEN = "0010" else
					CONV_STD_LOGIC_VECTOR( 239, 8 ) when ATTEN = "0001" else
					CONV_STD_LOGIC_VECTOR( 255, 8 );									-- nejhlasitejsi
					
	process ( CK443K )
		variable clk_counter : std_logic_vector(9 downto 0) := (others=>'0');
	begin
		if CK443K'event and CK443K = '1' then
			if clk_counter = CONV_STD_LOGIC_VECTOR( 0, 10 ) then
				clk_counter := DIVIDER;
				
				if iWAVE(23) = '0' then
					iWAVE <= "1" & "11" & (not iVOLUME) & "0000000000000";
				else
					iWAVE <= "0" & "00" & iVOLUME & "1111111111111";				
				end if;
				
			else 
				clk_counter := clk_counter - 1;
			end if;
		end if;
	end process;

	WAVE <= (others=>'0') when ATTEN = "1111" else SIGNED(iWAVE);
	
end RTL;

