--------------------------------------------------------------------------------
-- Company:        Jablotron s.r.o.
-- Engineer:       Hynek Sladky
--
-- Create Date:    10:29:19 02/04/07
-- Design Name:    CGA2VGA - scan line doubler
-- Module Name:    cga2vga - Behavioral
-- Project Name:   
-- Target Device:  Spartan3 - XC3S50TQ144-5
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
-- ToDo:
-- - prepocitat DCM na vstup 3.5MHz: vystup z DCM ma byt 35.468MHz
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cga2vga is
  Port (
    CLOCK: in std_logic;
    Rin: in std_logic;
    Gin: in std_logic;
    Bin: in std_logic;
    Yin: in std_logic;
    HSin: in std_logic;
    VSin: in std_logic;
    Rout: out std_logic;
    Gout: out std_logic;
    Bout: out std_logic;
    Yout: out std_logic;
    HSout: out std_logic;
    VSout: out std_logic
  );
end cga2vga;

architecture Behavioral of cga2vga is
  -- deklarace sampleru
  component sampler
    port (
      CLK: in std_logic;
      SAMPLE: in std_logic;
      EDGE: in std_logic;
      Din: in std_logic_vector (7 downto 0);
      Dout: out std_logic_vector (7 downto 0)
    );
  end component;
  -- konstanty
  -- vnitrni signaly
  -- FIFO a samplery
  signal FIFOin: std_logic_vector (5 downto 0);
  signal FIFO1: std_logic_vector (5 downto 0);
  signal FIFO2: std_logic_vector (5 downto 0);
  signal EDGE: std_logic;
  signal SEL: std_logic;
  signal FIFOd: std_logic_vector (7 downto 0);
  signal SMPL1: std_logic_vector (7 downto 0);
  signal SMPL2: std_logic_vector (7 downto 0);
  signal SMPLout: std_logic_vector (5 downto 0);
  -- 

begin
  -- funkce
  -- vstupni dvouurovnova FIFO
  FIFOin <= VSin & HSin & Yin & Bin & Gin & Rin;
  process (CLOCK) begin
    if CLOCK'event and CLOCK='0' then
      FIFO1 <= FIFOin;
    end if;
    if CLOCK'event and CLOCK='0' then
      FIFO2 <= FIFO1;
    end if;
  end process;
  -- detekce HSYN hrany
  EDGE <= FIFO1(4) and not FIFO2(4);
--  EDGE <= not FIFO1(4) and FIFO2(4);
  -- prepinani sample/play
  process (CLOCK) begin
    if CLOCK'event and CLOCK='0' and EDGE='1' then
      SEL <= not SEL;
    end if;
  end process;
  -- pripojeni dvou jednotek sample/play
  FIFOd <= EDGE & '0' & FIFO2;
  -- pripojeni sampleru
  sampler1: sampler
  port map (
    CLK => CLOCK,
    SAMPLE => SEL,
    EDGE => EDGE,
    Din => FIFOd,
    Dout => SMPL1
  );
  sampler2: sampler
  port map (
    CLK => CLOCK,
    SAMPLE => not SEL,
    EDGE => EDGE,
    Din => FIFOd,
    Dout => SMPL2
  );
  -- pripojeni vystupu pres multiplexer
  -- nezapomenout na KO pro stabilni vystup vzorku!
  process (CLOCK) begin
    if CLOCK'event and CLOCK='0' then
      --SMPLout <= SMPL1 when SEL='1' else SMPL2;
      if SEL='1' then
        SMPLout <= SMPL2 (5 downto 0);
      else
        SMPLout <= SMPL1 (5 downto 0);
      end if;
    end if;
  end process;
  -- vystup z modulu:
  -- vystupni signaly ze sampleru
  Rout <= not SMPLout(0);
  Gout <= not SMPLout(1);
  Bout <= not SMPLout(2);
  Yout <= not SMPLout(3);
  HSout <= SMPLout(4);
  VSout <= VSin;

  -- a to je vse, pratele...

end Behavioral;