-------------------------------------------------------------------------------- -- Company: Jablotron s.r.o. -- Engineer: Hynek Sladky -- -- Create Date: 10:58:20 02/04/07 -- Design Name: -- Module Name: sampler - Behavioral -- Project Name: -- Target Device: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity sampler is Port ( CLK: in std_logic; SAMPLE: in std_logic; EDGE: in std_logic; Din: in std_logic_vector (7 downto 0); Dout: out std_logic_vector (7 downto 0) ); end sampler; architecture Behavioral of sampler is -- pracovni signaly signal BUSout: std_logic_vector (7 downto 0); signal BUSaddr: std_logic_vector (13 downto 0); -- pamet vzorku component RAMB16_S9 generic ( INIT: bit_vector := X"000"; INIT_00: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1E: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2E: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3C: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_00: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07: bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; WRITE_MODE: string := "WRITE_FIRST"; SRVAL: bit_vector := X"000" ); port ( DO: out std_logic_vector (7 downto 0); DOP: out std_logic_vector (0 downto 0); ADDR: in std_logic_vector (10 downto 0); CLK: in std_ulogic; DI: in std_logic_vector (7 downto 0); DIP: in std_logic_vector (0 downto 0); EN: in std_ulogic; SSR: in std_ulogic; WE: in std_ulogic ); end component; begin -- pripojeni pameti samples: RAMB16_S9 generic map ( -- zda se, ze ulozeni bytu na adrese 0 je posledni dvojcisli na prvni radce... INIT => X"000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", WRITE_MODE => "WRITE_FIRST", SRVAL => X"000" ) port map ( DO => BUSout, -- data out --DOP => -- parity out ADDR => BUSaddr(13 downto 3), -- address CLK => CLK, -- synchronous clock DI => Din, -- data i DIP => "0", -- parity in EN => '1', -- chip enable SSR => '0', -- reset WE => SAMPLE -- write enable ); -- generovani adresy process (CLK) begin if CLK'event and CLK='0' then if (BUSout(7)='1' and SAMPLE='0') or EDGE='1' then BUSaddr <= "00000000000000"; elsif SAMPLE='1' then BUSaddr <= BUSaddr + "0000000000100"; else BUSaddr <= BUSaddr + "0000000001000"; end if; end if; end process; Dout <= BUSout; end Behavioral;